1. Field of the Invention
The present invention relates to a memory capacitor and a fabrication method thereof, and more particularly, to a trench capacitor and a fabrication method thereof.
2. Description of the Related Art
Due to minimization of devices, device dimensions are required shrinkage. For memory devices with capacitors, areas for fabrication of capacitors also are continuously reduced. A trench capacitor memory device is a device with a capacitor formed in the substrate that it solves the issue of device minimization.
The prior art method of fabricating a trench capacitor is shown in FIG. 1A. Referring to FIG. 1A, a silicon oxide layer 102 and a silicon nitride layer 104 are sequentially formed over a substrate 100. Then, an etch process is performed to remove portions of the silicon oxide layer 102 and the silicon nitride layer 104 to form openings 106 which expose the surface of the substrate 100.
Referring to FIG. 1B, a portion of the substrate 100 is removed to form a plurality of trenches 108 therein by using the silicon oxide layer 102 and the silicon nitride layer 104 as an etch mask. Then, a doped region 110 is formed in the substrate 100 of the surface of the trenches 108.
Referring to FIG. 1C, an oxide/nitride/oxide (ONO) layer 112 is formed over the surface of the trenches 108. A doped polysilicon layer 114 is deposited in the trenches 108. A chemical-mechanical polish (CMP) process then is performed to remove a portion of the doped polysilicon layer 114 until the surface of the silicon nitride layer 104 is exposed.
Referring to FIG. 1D, the silicon oxide layer 102 and the silicon nitride layer 104 are removed. Moreover, a portion of the doped polysilicon layer 114 is removed to expose the surface of the substrate 100.
In the prior art method mentioned above, the step shown in FIG. 1D of removing silicon oxide layer 102, the silicon nitride layer 104 and the portion of the doped polysilicon layer 114 to expose the surface of the substrate 100 may damage the surface of the ONO layer 112. That causes leakage currents and affects the process reliability and yields. After the step shown in FIG. 1D, the surface of the ONO layer 112 is also exposed. In the subsequent processes, such as the doping process and the etch process to define the active area and form the device, the surface of the ONO layer 112 of the trench capacitor is subject to damage as well.
U.S. Pat. No. 6,661,050 B2 discloses a memory cell structure with a trench capacitor and a fabrication method thereof. U.S. Pat. No. 6,808,980 B2 discloses a trench-type one-transistor random access memory (1T-RAM) structure and a fabrication method thereof. However, the patents can be more complicated for the process, and can't effectively solve the above-mentioned question.